1. Field of the Invention
The present invention generally relates to a ferroelectric memory, and more particularly, to a ferroelectric memory using as a storage medium a ferroelectric capacitor composed of a ferroelectric material.
2. Description of the Related Art
Conventionally proposed ferroelectric memories include a ferroelectric memory comprising a 1T1C-type memory cell using one transistor and one ferroelectric capacitor, and a ferroelectric memory comprising a 2T2C-type memory cell using two transistors and two ferroelectric capacitors. These ferroelectric memories are popular in separate markets: the former ferroelectric memory is popular in a market where a high density and a large capacity are required, and the latter ferroelectric memory is popular in a market where a high reliability is required.
FIG. 1 is a circuit diagram showing a main part of an example of the conventional ferroelectric memory comprising the 2T2C-type memory cell. FIG. 1 shows a word line WL, bit lines BL and XBL, a plate line PL, and a 2T2C-type memory cell MC. The 2T2C-type memory cell MC includes ferroelectric capacitors FC1 and FC2 forming storage media, and nMOS transistors M1 and M2 forming access transistors.
FIG. 1 also shows sense amplifier drive voltage lines SAP and SAN, and a differential sense amplifier SA. The differential sense amplifier SA includes pMOS transistors M3 and M4 forming pull-up elements, and nMOS transistors M5 and M6 forming pull-down elements.
Besides, in FIG. 1, “0” indicates a downward polarization of the ferroelectric capacitor, and “1” indicates an upward polarization of the ferroelectric capacitor. In FIG. 2, “0” and “1” are represented by positions A and B, respectively, in a hysteresis loop of the ferroelectric capacitor. When the bit lines BL and XBL are maintained at a grounding voltage VSS, and the plate line PL is driven from the grounding voltage VSS to a power supply voltage VDD, conditions of “0” and “1” correspond respectively to a case where an effective capacitance of the ferroelectric capacitor is small, and a case where an effective capacitance of the ferroelectric capacitor is large.
FIG. 3 is a waveform diagram exemplifying a readout operation when the conventional ferroelectric memory shown in FIG. 1 adopts a plate-line drive readout method. In an example shown in FIG. 3, the memory cell MC is selected in a case where data “0” is stored in the ferroelectric capacitor FC1, and data “1” is stored in the ferroelectric capacitor FC2.
In this readout method, prior to a readout (Read) period, a potential of the word line WL is VSS so that the nMOS transistors M1 and M2 are OFF. Also, a potential of the sense amplifier drive voltage line SAP is VSS, and a potential of the sense amplifier drive voltage line SAN is VDD so that the sense amplifier SA is inactive. Further, a potential of the plate line PL is VSS, and the bit lines BL and XBL are precharged at VSS.
In the readout period, the potential of the word line WL is made VDD so that the nMOS transistors M1 and M2 are turned ON; thereafter, the potential of the plate line PL is made VDD. Consequently, the potentials of the bit lines BL and XBL rise slightly so that a differential voltage occurs between the bit lines BL and XBL.
In this example, since the ferroelectric capacitor FC1 stores the data “0”, the ferroelectric capacitor FC1 does not cause a polarization inversion even when the potential of the plate line PL is pulled up from VSS to VDD; accordingly, the effective capacitance of the ferroelectric capacitor FC1 becomes small. On the other hand, the ferroelectric capacitor FC2 causes a polarization inversion when the potential of the plate line PL is pulled up from VSS to VDD; accordingly, the effective capacitance of the ferroelectric capacitor FC2 becomes large. Consequently, the potential of the bit line BL becomes smaller than the potential of the bit line XBL.
Then, the potential of the sense amplifier drive voltage line SAP is made VDD, and the potential of the sense amplifier drive voltage line SAN is made VSS so that the sense amplifier SA is activated. At this point, since the potential of the bit line BL is smaller than the potential of the bit line XBL, a differential operation of the sense amplifier SA causes the pMOS transistor M3 to be OFF, the pMOS transistor M4 to be ON, the nMOS transistor M5 to be ON, and the nMOS transistor M6 to be OFF. Accordingly, the bit line BL is pulled down to VSS, and the bit line XBL is pulled up to VDD.
In this state, a write-back (Write-Back) period follows the readout period. In the write-back period, the potential of the plate line PL is pulled down to VSS, and a write-back is performed to the ferroelectric capacitors FC1 and FC2. When the write-back period finishes, the potential of the word line WL is made VSS so that the nMOS transistors M1 and M2 are turned OFF. Also, the potential of the sense amplifier drive voltage line SAP is made VSS, and the potential of the sense amplifier drive voltage line SAN is made VDD so that the sense amplifier SA is deactivated. Further, the bit lines BL and XBL are precharged at VSS.
As described above, in the plate-line drive readout method exemplified in FIG. 3, the plate line PL is driven upon performing a readout; and based on a difference between the effective capacitances of the ferroelectric capacitors FC1 and FC2 having different data, a differential voltage is generated between the bit lines BL and XBL, thereby performing the readout.
FIG. 4 is a waveform diagram exemplifying a readout operation when the conventional ferroelectric memory shown in FIG. 1 adopts a plateline non-drive readout method (H. Koike et al., Journal of Solid-State Circuits, vol.31, no.11, pp. 1625-1634, 1997). In an example shown in FIG. 4, data “0” is stored in the ferroelectric capacitor FC1, and data “1” is stored in the ferroelectric capacitor FC2.
In this readout method, the potential of the plate line PL is fixed at VDD/2. Prior to a readout (Read) period, the potential of the word line WL is VSS so that the nMOS transistors M1 and M2 are OFF. Besides, the potentials of the sense amplifier drive voltage lines SAP and SAN are VDD/2, and the potentials of the bit lines BL and XBL are VDD/2.
In the readout period, the potential of the sense amplifier drive voltage line SAP is made VSS, and the potential of the sense amplifier drive voltage line SAN is made VDD so that the sense amplifier SA is deactivated. Also, the potentials of the bit lines BL and XBL are made VSS. Thereafter, the potential of the word line WL is made VDD so that the nMOS transistors M1 and M2 are turned ON. Consequently, the potentials of the bit lines BL and XBL rise slightly so that a differential voltage occurs between the bit lines BL and XBL (the potential of the bit line BL being smaller than the potential of the bit line XBL).
Then, the potential of the sense amplifier drive voltage line SAP is made VDD, and the potential of the sense amplifier drive voltage line SAN is made VSS so that the sense amplifier SA is activated. Consequently, the potential of the bit line BL is pulled down to VSS, and the potential of the bit line XBL is pulled up to VDD. In this state, a write-back (Write-Back) period follows the readout period. Before the write-back period finishes, the potentials of the sense amplifier drive voltage lines SAP and SAN are made VDD/2, and subsequently, the potentials of the bit lines BL and XBL are made VDD/2. When the write-back period finishes, the potential of the word line WL is made VSS.
As described above, in the plate-line non-drive readout method exemplified in FIG. 4, the plate line PL is not driven, but is fixed at VDD/2, upon performing a readout; and based on the potentials of the bit lines BL and XBL precharged at VSS, and a charge sharing between storage nodes S1 and S2 (shown in FIG. 1) set at VDD/2, a readout is performed, thereby shortening a readout access time.
FIG. 5 is a waveform diagram exemplifying a readout operation when the conventional ferroelectric memory shown in FIG. 1 adopts a bit-line drive readout method (H. Hirano et al., Journal of Solid-State Circuits, vol.32, no.5, pp.649-654, 1997). In an example shown in FIG. 5, data “0” is stored in the ferroelectric capacitor FC1, and data “1” is stored in the ferroelectric capacitor FC2.
In this readout method, prior to a readout (Read) period, the potential of the word line WL is VSS so that the nMOS transistors M1 and M2 are OFF. Also, the potential of the sense amplifier drive voltage line SAP is VSS, and the potential of the sense amplifier drive voltage line SAN is VDD so that the sense amplifier SA is inactive. Further, the potential of the plate line PL is VSS, and the potentials of the bit lines BL and XBL are VSS. Immediately before the readout period, the bit lines BL and XBL are precharged at VDD.
Then, in the readout period, the potential of the word line WL is made VPP (a voltage boosted from VDD) so that the nMOS transistors M1 and M2 are turned ON. Consequently, the potentials of the bit lines BL and XBL rise slightly so that a differential voltage occurs between the bit lines BL and XBL (the potential of the bit line BL being smaller than the potential of the bit line XBL).
Thereafter, the potential of the sense amplifier drive voltage line SAP is made VDD, and the potential of the sense amplifier drive voltage line SAN is made VSS so that the sense amplifier SA is activated. Consequently, the potential of the bit line BL is pulled down to VSS, and the potential of the bit line XBL is pulled up to VDD.
In this state, a write-back (Write-Back) period follows the readout period. In the write-back period, the potential of the plate line PL is pulled down to VSS, up to VDD, and down to VSS, and a write-back is performed to the ferroelectric capacitors FC1 and FC2. When the write-back period finishes, the potential of the word line WL is made VSS so that the nMOS transistors M1 and M2 are turned OFF. Also, the potential of the sense amplifier drive voltage line SAP is made VSS, and the potential of the sense amplifier drive voltage line SAN is made VDD so that the sense amplifier SA is deactivated. Further, the bit lines BL and XBL are made VSS.
As described above, in the bit-line drive readout method exemplified in FIG. 5, the plate line PL is not driven upon performing a readout, but the bit lines BL and XBL are precharged at VDD; and according to a difference between discharge amounts of the bit lines BL and XBL which originates from a difference between the equivalent capacitances of the ferroelectric capacitors FC1 and FC2, the readout is performed. Therefore, although the plate line PL needs to be driven upon performing a write-back of data after the readout, an access time of the readout can be shortened in comparison with the plate-line drive readout method exemplified in FIG. 3.
Since the plate-line drive readout method exemplified in FIG. 3 includes driving the plate line PL upon performing a readout which involves a large CR delay, the plate-line drive readout method exemplified in FIG. 3 has a problem of a prolonged readout access time.
Since the plate-line non-drive readout method exemplified in FIG. 4 impresses only VDD/2 to the ferroelectric capacitors FC1 and FC2, a data writing cannot be performed with the full power supply voltage VDD, which does not conform to low voltage conditions. Additionally, after a data writing is performed, the storage nodes S1 and S2 are discharged to the grounding voltage VSS by leakage currents of diodes parasitic on the nMOS transistors M1 and M2; thus, the storage nodes S1 and S2 need to be refreshed periodically. These problems make serious obstacles for an actual operation of a memory, which hinders a utilization of this method.
Since the bit-line drive readout method exemplified in FIG. 5 includes precharging the bit lines BL and XBL at VDD before a readout, the boosted voltage VPP needs to be impressed to the word line WL. Therefore, the bit-line drive readout method necessitates a circuit for boosting VDD to VPP, thereby causing a problem of an enlarged circuit area, and power consumption.